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fpga:acex_devel_en 2007/02/07 07:49 fpga:acex_devel_en 2007/02/07 07:56 version actuelle
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You can find here a small //PS// (Passive Serial) interface I've designed to interface the ACEX board to any x86 PC equipped with a parallel port. You can find here a small //PS// (Passive Serial) interface I've designed to interface the ACEX board to any x86 PC equipped with a parallel port.
-Schematics (coming soon) FIXME+Schematics are available below.
 +
 +{{ :fpga:p_serial.png |:fpga:p_serial.png}}
This very simple interface only uses a 74HCT05 (or 74LS05). These open drain inverters make the 5V(parallel port)/3.3V(FPGA) voltage translation. DCLK and DATA0 requires pull-up resistors (tied to FPGA_VCC_IO 3.3V) because they are not available on the ACEX board. This very simple interface only uses a 74HCT05 (or 74LS05). These open drain inverters make the 5V(parallel port)/3.3V(FPGA) voltage translation. DCLK and DATA0 requires pull-up resistors (tied to FPGA_VCC_IO 3.3V) because they are not available on the ACEX board.
 
fpga/acex_devel_en.txt · Dernière modification: 2007/02/07 07:56 par stellae
 
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