|
[[stellae:wiki]]
|
Différences
Cette page vous donne les différences entre la révision choisie et la version actuelle de la page.
| fpga:acex_devel_en 2007/02/07 07:49 | fpga:acex_devel_en 2007/02/07 07:56 version actuelle | ||
|---|---|---|---|
| Ligne 33: | Ligne 33: | ||
| You can find here a small //PS// (Passive Serial) interface I've designed to interface the ACEX board to any x86 PC equipped with a parallel port. | You can find here a small //PS// (Passive Serial) interface I've designed to interface the ACEX board to any x86 PC equipped with a parallel port. | ||
| - | Schematics (coming soon) FIXME | + | Schematics are available below. |
| + | |||
| + | {{ :fpga:p_serial.png |:fpga:p_serial.png}} | ||
| This very simple interface only uses a 74HCT05 (or 74LS05). These open drain inverters make the 5V(parallel port)/3.3V(FPGA) voltage translation. DCLK and DATA0 requires pull-up resistors (tied to FPGA_VCC_IO 3.3V) because they are not available on the ACEX board. | This very simple interface only uses a 74HCT05 (or 74LS05). These open drain inverters make the 5V(parallel port)/3.3V(FPGA) voltage translation. DCLK and DATA0 requires pull-up resistors (tied to FPGA_VCC_IO 3.3V) because they are not available on the ACEX board. | ||
